pipeline architecture中文什么意思

發(fā)音:

用"pipeline architecture"造句

管線結(jié)構(gòu)

architecture: n. 1.建筑學(xué)。 2.建筑(樣式、風(fēng)格)；建筑物。 3 ...
architecture pipeline: 管線結(jié)構(gòu)
in the pipeline: 在途中, 在進(jìn)行中
pipeline: 導(dǎo)管; 工藝過(guò)程; 供給系統(tǒng); 管道，管線; 管道跨越; 管道流; 管道路; 管道系; 管路; 建設(shè)管線; 廉線; 匿名消息來(lái)源; 情報(bào)來(lái)源; 渠管; 商品供應(yīng)線; 輸油管; 水管大作戰(zhàn); 裝管道
pipeline in the: 編審中

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例句與用法

This paper introduces the history of the gpu firstly , and then it analyses the pipeline architecture of gpu . finally , it introduces several types of program languages of gpu
本文首先介紹了可編程圖形硬件的發(fā)展，然后分析了它的流水線結(jié)構(gòu)，最后介紹了幾種最新的編程語(yǔ)言。
And it presents the method that the filter is analyze to lifting process . we use the folding and pipeline architecture to deal with this kind of novel dwt
本論文提出一種根據(jù)jpeg2000標(biāo)準(zhǔn)將9 7濾波器分解為提升過(guò)程矩陣乘積的形式，使用流水線的思想的新型離散小波變換結(jié)構(gòu)。
After analyzing and comparing different partition rules , md32 pipeline architecture is finally defined , which meets the required instruction function , frequency and timing spec of md32 . a complete set of creative design method for risc / dsp md32 micro - architecture is presented , such as parallel design , internal pipeline , central control , etc . thanks to the adoption of these design methodology , control path and data path are separated , circuit delay is reduced , and complex instruction operations are balanced among multiple pipeline stages
它們將若干復(fù)雜指令操作均勻分配在幾個(gè)流水節(jié)拍內(nèi)完成，實(shí)現(xiàn)了任意窗口尋址等復(fù)雜指令操作，將整個(gè)處理器的數(shù)據(jù)通路與控制通路分離，減小了電路時(shí)延，從而滿足了risc dsp不同指令功能和系統(tǒng)時(shí)鐘頻率的要求，構(gòu)成了統(tǒng)一的、緊密聯(lián)系的、協(xié)調(diào)的md32系統(tǒng)結(jié)構(gòu)。
The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu , and dwells on 64 - bit vega cpu characteristic , and details the eda technology and the main flow of asic design , and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation , and details cache architecture and mmu . the master dissertation dwells on virtual address translating into physical address , instruction cache finding address and instruction fetching , too
詳細(xì)的闡述了64位vegacpu的特點(diǎn)，闡述了eda技術(shù)和asic設(shè)計(jì)的主要流程，闡述了vegacpu流水線結(jié)構(gòu)、流水線操作、流水線暫停和異常處理，虛擬指令地址的結(jié)構(gòu)和產(chǎn)生， mmu結(jié)構(gòu)，包括指令tlb結(jié)構(gòu)和虛擬指令地址向物理指令地址的生成流程， cache結(jié)構(gòu)，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結(jié)構(gòu)，以及指令的獲取流程。

其他語(yǔ)言

pipeline architecture перевод

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pipeline architecture中文什么意思

例句與用法

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